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1200 MHz to 2400 MHz Quadrature Modulator with 1550 MHz to 2150 MHz Frac-N PLL and Integrated VCO
ADRF6702
FEATURES
IQ modulator with integrated fractional-N PLL Output frequency range: 1200 MHz to 2400 MHz Internal LO frequency range: 1550 MHz to 2150 MHz Output P1dB: 13.1 dBm @ 2140 MHz Output IP3: 29.1 dBm @ 2140 MHz Noise floor: -157.8 dBm/Hz @ 2140 MHz Baseband bandwidth: 750 MHz (3 dB) SPI serial interface for PLL programming Integrated LDOs and LO buffer Power supply: 5 V/240 mA 40-lead 6 mm x 6 mm LFCSP
dynamic range and linearity. The integration of the IQ modulator, PLL, and VCO provides for significant board savings and reduces the BOM and design complexity. The integrated fractional-N PLL/synthesizer generates a 2x fLO input to the IQ modulator. The phase detector together with an external loop filter is used to control the VCO output. The VCO output is applied to a quadrature divider. To reduce spurious components, a sigma-delta (-) modulator controls the programmable PLL divider. The IQ modulator has wideband differential I and Q inputs, which support baseband as well as complex IF architectures. The single-ended modulator output is designed to drive a 50 load impedance and can be disabled. The ADRF6702 is fabricated using an advanced silicongermanium BiCMOS process. It is available in a 40-lead, exposed-paddle, Pb-free, 6 mm x 6 mm LFCSP package. Performance is specified from -40C to +85C. A lead-free evaluation board is available. Table 1.
Part No. ADRF6702 Internal LO Range 1550 MHz 2150 MHz IQ Modulator 3 dB RF Output Range 1200 MHz 2400 MHz
APPLICATIONS
Cellular communications systems GSM/EDGE, CDMA2000, W-CDMA, TD-SCDMA, LTE Broadband wireless access systems Satellite modems
GENERAL DESCRIPTION
The ADRF6702 provides a quadrature modulator and synthesizer solution within a small 6 mm x 6 mm footprint while requiring minimal external components. The ADRF6702 is designed for RF outputs from 1200 MHz to 2400 MHz. The low phase noise VCO and high performance quadrature modulator make the ADRF6702 suitable for next generation communication systems requiring high signal
VCC7
34
FUNCTIONAL BLOCK DIAGRAM
VCC6
29
VCC5
27
VCC4
22
VCC3
17
VCC2
10
VCC1
1
LOSEL 36 LON 37
BUFFER
ADRF6702
DIVIDER /2 2:1 MUX
40 9 2
DECL3 DECL2 DECL1
LOP 38
BUFFER
DATA 12 CLK 13 LE 14
SPI INTERFACE
FRACTION REG
MODULUS
INTEGER REG
THIRD-ORDER FRACTIONAL INTERPOLATOR x2 N COUNTER 21 TO 123 MUX TEMP SENSOR
4 7
REFIN 6 /2 /4 MUXOUT 8
PRESCALER /2 CHARGE PUMP 250A, 500A (DEFAULT), 750A, 1000A
24 5 3
VCO CORE
18
QP QN IN IP
/2 0/90
19 32 33
- PHASE + FREQUENCY DETECTOR
11 15 20 21 23 25 28 30 31 35
39
16
26
08568-001
GND NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
NC
RSET
CP VTUNE ENOP RFOUT
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
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ADRF6702 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Characteristics ................................................................ 6 Absolute Maximum Ratings............................................................ 7 ESD Caution .................................................................................. 7 Pin Configuration and Function Descriptions ............................. 8 Typical Performance Characteristics ........................................... 10 Theory of Operation ...................................................................... 15 PLL + VCO .................................................................................. 15 Basic Connections for Operation ............................................. 15 External LO ................................................................................. 15 Loop Filter ................................................................................... 16 DAC-to-IQ Modulator Interfacing .......................................... 17 Adding a Swing-Limiting Resistor ........................................... 17 IQ Filtering .................................................................................. 18 Baseband Bandwidth ................................................................. 18 Device Programming and Register Sequencing..................... 18 Register Summary .......................................................................... 19 Register Description....................................................................... 20 Register 0--Integer Divide Control (Default: 0x0001C0) .... 20 Register 1--Modulus Divide Control (Default: 0x003001) .. 21 Register 2--Fractional Divide Control (Default: 0x001802) 21 Register 3--- Modulator Dither Control (Default: 0x10000B) .................................................................................... 22 Register 4--PLL Charge Pump, PFD, and Reference Path Control (Default: 0x0AA7E4)................................................... 23 Register 5--LO Path and Modulator Control (Default: 0x0000D5) ................................................................................... 25 Register 6--VCO Control and VCO Enable (Default: 0x1E2106) .................................................................................... 26 Register 7--External VCO Enable ........................................... 26 Characterization Setups ................................................................. 27 Evaluation Board ............................................................................ 29 Evaluation Board Control Software ......................................... 29 Outline Dimensions ....................................................................... 34 Ordering Guide .......................................................................... 34
REVISION HISTORY
4/11--Revision 0: Initial Version
Rev. 0 | Page 2 of 36
ADRF6702 SPECIFICATIONS
VS = 5 V; TA = 25C; baseband I/Q amplitude = 1 V p-p differential sine waves in quadrature with a 500 mV dc bias; baseband I/Q frequency (fBB) = 1 MHz; fPFD = 38.4 MHz; fREF = 153.6 MHz at +4 dBm Re:50 (1 V p-p); 130 kHz loop filter, unless otherwise noted. Table 2.
Parameter OPERATING FREQUENCY RANGE RF OUTPUT = 1850 MHz Nominal Output Power IQ Modulator Voltage Gain OP1dB Carrier Feedthrough Sideband Suppression Quadrature Error I/Q Amplitude Balance Second Harmonic Third Harmonic Output IP2 Output IP3 Noise Floor RF OUTPUT = 1960 MHz Nominal Output Power IQ Modulator Voltage Gain OP1dB Carrier Feedthrough Sideband Suppression Quadrature Error I/Q Amplitude Balance Second Harmonic Third Harmonic Output IP2 Output IP3 Noise Floor RF OUTPUT = 2140 MHz Nominal Output Power IQ Modulator Voltage Gain OP1dB Carrier Feedthrough Sideband Suppression Quadrature Error I/Q Amplitude Balance Second Harmonic Third Harmonic Output IP2 Output IP3 Noise Floor SYNTHESIZER SPECIFICATIONS Internal LO Range Figure of Merit (FOM) 1 Test Conditions/Comments IQ modulator (3 dB RF output range) PLL LO range RFOUT pin Baseband VIQ = 1 V p-p differential RF output divided by baseband input voltage Min 1200 1550 4 0 13.5 -41.2 -43.7 1 0.02 -62.2 -50.6 56 31 -156.6 4.1 0.1 13.6 -40.6 -53.9 +0.7/-1.7 0.03 -74.6 -54.1 66.4 30.1 -156.5 3.8 -0.2 13.1 -46.8 -44.4 1 0.02 -71.8 -57.3 70.4 29.1 -157.8 1550 -220.5 2150 Typ Max 2400 2150 Unit MHz MHz dBm dB dBm dBm dBc Degrees dB dBc dBc dBm dBm dBm/Hz dBm dB dBm dBm dBc Degrees dB dBc dBc dBm dBm dBm/Hz dBm dB dBm dBm dBc Degrees dB dBc dBc dBm dBm dBm/Hz MHz dBc/Hz/Hz
POUT - P (fLO (2 x fBB)) POUT - P (fLO (3 x fBB)) f1BB = 3.5 MHz, f2BB = 4.5 MHz, POUT -2 dBm per tone f1BB = 3.5 MHz, f2BB = 4.5 MHz, POUT -2 dBm per tone I/Q inputs = 0 V differential with 500 mV dc bias, 20 MHz carrier offset RFOUT pin Baseband VIQ = 1 V p-p differential RF output divided by baseband input voltage
POUT - P (fLO (2 x fBB)) POUT - P (fLO (3 x fBB)) f1BB = 3.5 MHz, f2BB = 4.5 MHz, POUT -2 dBm per tone f1BB = 3.5 MHz, f2BB = 4.5 MHz, POUT -2 dBm per tone I/Q inputs = 0 V differential with 500 mV dc bias, 20 MHz carrier offset RFOUT pin Baseband VIQ = 1 V p-p differential RF output divided by baseband input voltage
POUT - P (fLO (2 x fBB)) POUT - P (fLO (3 x fBB)) f1BB = 3.5 MHz, f2BB = 4.5 MHz, POUT -2 dBm per tone f1BB = 3.5 MHz, f2BB = 4.5 MHz, POUT -2 dBm per tone) I/Q inputs = 0 V differential with 500 mV dc bias, 20 MHz carrier offset Synthesizer specifications referenced to the modulator output
Rev. 0 | Page 3 of 36
ADRF6702
Parameter REFERENCE CHARACTERISTICS REFIN Input Frequency REFIN Input Capacitance Phase Detector Frequency MUXOUT Output Level MUXOUT Duty Cycle CHARGE PUMP Charge Pump Current Output Compliance Range PHASE NOISE (FREQUENCY = 1850 MHz, fPFD = 38.4 MHz) Programmable to 250 A, 500 A, 750 A, 1000 A 1 Closed loop operation (see Figure 34 for loop filter design) 10 kHz offset 100 kHz offset 1 MHz offset 10 MHz offset 1 kHz to 10 MHz integration bandwidth fPFD/2 fPFD fPFD x 2 fPFD x 3 fPFD x 4 Closed loop operation (see Figure 34 for loop filter design) 10 kHz offset 100 kHz offset 1 MHz offset 10 MHz offset 1 kHz to 10 MHz integration bandwidth fPFD/2 fPFD fPFD x 2 fPFD x 3 fPFD x 4 Closed loop operation (see Figure 34 for loop filter design) 10 kHz offset 100 kHz offset 1 MHz offset 10 MHz offset 1 kHz to 10 MHz integration bandwidth fPFD/2 fPFD fPFD x 2 fPFD x 3 fPFD x 4 Measured at RFOUT, frequency = 2140 MHz Second harmonic Third harmonic LOP, LON Divide by 2 circuit in LO path enabled Divide by 2 circuit in LO path disabled 2x LO or 1x LO mode, into a 50 load, LO buffer enabled Externally applied 2x LO, PLL disabled Externally applied 2x LO, PLL disabled
Rev. 0 | Page 4 of 36
Test Conditions/Comments REFIN, MUXOUT pins
Min 12
Typ
Max 160
Unit MHz pF MHz V V % A V
4 20 Low (lock detect output selected) High (lock detect output selected) 2.7 50 500 2.8 40 0.25
Integrated Phase Noise Reference Spurs
-110.8 -105.8 -124.6 -144.2 0.27 -112 -84 -87 -93 -90
dBc/Hz dBc/Hz dBc/Hz dBc/Hz rms dBc dBc dBc dBc dBc
PHASE NOISE (FREQUENCY =
1960 MHz, fPFD = 38.4 MHz)
Integrated Phase Noise Reference Spurs
-108.5 -104.2 -125.1 -144.7 0.25 -110 -83 -97 -91 -97
dBc/Hz dBc/Hz dBc/Hz dBc/Hz rms dBc dBc dBc dBc dBc
PHASE NOISE (FREQUENCY =
2140 MHz, fPFD = 38.4 MHz)
Integrated Phase Noise Reference Spurs
-107.5 -102.7 -126.1 -144.8 0.25 -111 -86 -88 -91 -99 -47 -74 1550 3100 1 0 50 2150 4300
dBc/Hz dBc/Hz dBc/Hz dBc/Hz rms dBc dBc dBc dBc dBc dBc dBc MHz MHz dBm dBm
RF OUTPUT HARMONICS
LO INPUT/OUTPUT Output Frequency Range LO Output Level at 1960 MHz LO Input Level LO Input Impedance
ADRF6702
Parameter BASEBAND INPUTS I and Q Input DC Bias Level Bandwidth Test Conditions/Comments IP, IN, QP, QN pins 400 POUT -7 dBm, RF flatness of IQ modulator output calibrated out 0.5 dB 3 dB 500 350 750 920 1 1.4 0 0.1 5 VPTAT voltage measured at MUXOUT TA = 25C, RL 10 k (LO buffer disabled) TA = -40C to +85C, RL 10 k VCC1, VCC2, VCC3, VCC4, VCC5, VCC6, VCC7 4.75 Normal Tx mode (PLL and IQMOD enabled, LO buffer disabled) Tx mode using external LO input (internal VCO/PLL disabled) Tx mode with LO buffer enabled Power-down mode 1.64 3.9 5 240 130 290 22 5.25 3.3 0.7 600 mV MHz MHz pF V V A pF V mV/C V mA mA mA A Min Typ Max Unit
Differential Input Impedance Differential Input Capacitance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINH/IINL Input Capacitance, CIN TEMPERATURE SENSOR Output Voltage Temperature Coefficient POWER SUPPLIES Voltage Range Supply Current
CLK, DATA, LE, ENOP, LOSEL
1
The figure of merit (FOM) is computed as phase noise (dBc/Hz) - 10log10(fPFD) - 20log10(fLO/fPFD). The FOM was measured across the full LO range, with fREF = 80 MHz, fREF power = 10 dBm (500 V/s slew rate) with a 40 MHz fPFD. The FOM was computed at 50 kHz offset.
Rev. 0 | Page 5 of 36
ADRF6702
TIMING CHARACTERISTICS
Table 3.
Parameter t1 t2 t3 t4 t5 t6 t7 Limit 20 10 10 25 25 10 20 Unit ns min ns min ns min ns min ns min ns min ns min
t4
CLK
Test Conditions/Comments LE to CLK setup time DATA to CLK setup time DATA to CLK hold time CLK high duration CLK low duration CLK to LE setup time LE pulse width
t5
t2
DATA DB23 (MSB) DB22
t3
DB2 (CONTROL BIT C3) DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1)
t6
LE
t7
t1
08568-002
Figure 2. Timing Diagram
Rev. 0 | Page 6 of 36
ADRF6702 ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Supply Voltage (VCC1 to VCC7) Digital I/O, CLK, DATA, LE LOP, LON IP, IN, QP, QN REFIN JA (Exposed Paddle Soldered Down)1 Maximum Junction Temperature Operating Temperature Range Storage Temperature Range
1
Rating 5.5 V -0.3 V to +3.6 V 18 dBm -0.5 V to +1.5 V -0.3 V to +3.6 V 35C/W 150C -40C to +85C -65C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
Per JDEC standard JESD 51-2.
Rev. 0 | Page 7 of 36
ADRF6702 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
40 39 38 37 36 35 34 33 32 31 DECL3 VTUNE LOP LON LOSEL GND VCC7 IP IN GND
VCC1 1 DECL1 2 CP 3 GND 4 RSET 5 REFIN 6 GND 7 MUXOUT 8 DECL2 9 VCC2 10
PIN 1 INDICATOR
ADRF6702
TOP VIEW (Not to Scale)
30 29 28 27 26 25 24 23 22 21
GND VCC6 GND VCC5 RFOUT GND NC GND VCC4 GND
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. 1, 10, 17, 22, 27, 29, 34 Mnemonic VCC1, VCC2, VCC3, VCC4, VCC5, VCC6, VCC7 DECL1 CP Description Power Supply Pins. The power supply voltage range is 4.75 V to 5.25 V. Drive all of these pins from the same power supply voltage. Decouple each pin with 100 pF and 0.1 F capacitors located close to the pin. Decoupling Node for Internal 3.3 V LDO. Decouple this pin with 100 pF and 0.1 F capacitors located close to the pin. Charge Pump Output Pin. Connect VTUNE to this pin through the loop filter. If an external VCO is being used, connect the output of the loop filter to the VCO's voltage control pin. The PLL control loop should then be closed by routing the VCO's frequency output back into the ADRF6702 through the LON and LOP pins. Ground. Connect these pins to a low impedance ground plane. Do not connect to this pin. Charge Pump Current. The nominal charge pump current can be set to 250 A, 500 A, 750 A, or 1000 A using DB10 and DB11 of Register 4 and by setting DB18 to 0 (CP reference source). In this mode, no external RSET is required. If DB18 is set to 1, the four nominal charge pump currents (INOMINAL) can be externally tweaked according to the following equation:
217.4 x I CP R SET = I NOMINAL - 37.8
2 3
4, 7, 11, 15, 20, 21, 23, 25, 28, 30, 31, 35 24 5
GND NC RSET
6
REFIN
8
MUXOUT
9 12
DECL2 DATA
where ICP is the base charge pump current in microamps. For further details on the charge pump current, see the Register 4--PLL Charge Pump, PFD, and Reference Path Control section. Reference Input. The nominal input level is 1 V p-p. Input range is 12 MHz to 160 MHz. This pin has high input impedance and should be ac-coupled. If REFIN is being driven by laboratory test equipment, the pin should be externally terminated with a 50 resistor (place the ac-coupling capacitor between the pin and the resistor). When driven from an 50 RF signal generator, the recommended input level is 4 dBm. Multiplexer Output. This output allows a digital lock detect signal, a voltage proportional to absolute temperature (VPTAT), or a buffered, frequency-scaled reference signal to be accessed externally. The output is selected by programming DB21 to DB23 in Register 4. Decoupling Node for 2.5 V LDO. Connect 100 pF, 0.1 F, and 10 F capacitors between this pin and ground. Serial Data Input. The serial data input is loaded MSB first with the three LSBs being the control bits.
Rev. 0 | Page 8 of 36
08568-003
NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 2. THE EXPOSED PADDLE SHOULD BE SOLDERED TO A LOW IMPEDANCE GROUND PLANE.
GND DATA CLK LE GND ENOP VCC3 QP QN GND
11 12 13 14 15 16 17 18 19 20
ADRF6702
Pin No. 13 Mnemonic CLK Description Serial Clock Input. This serial clock input is used to clock in the serial data to the registers. The data is latched into the 24-bit shift register on the CLK rising edge. Maximum clock frequency is 20 MHz. Latch Enable. When the LE input pin goes high, the data stored in the shift registers is loaded into one of the six registers, the relevant latch being selected by the first three control bits of the 24-bit word. Modulator Output Enable/Disable. See Table 6. Modulator Baseband Inputs. Differential in-phase and quadrature baseband inputs. These inputs should be dc-biased to 0.5 V. RF Output. Single-ended, 50 internally biased RF output. RFOUT must be ac-coupled to its load. LO Select. This digital input pin determines whether the LOP and LON pins operate as inputs or outputs. This pin should not be left floating. LOP and LON become inputs if the LOSEL pin is set low and the LDRV bit of Register 5 is set low. External LO drive must be a 2x LO. In addition to setting LOSEL and LDRV low and providing an external 2x LO, the LXL bit of Register 5 (DB4) must be set to 1 to direct the external LO to the IQ modulator. LON and LOP become outputs when LOSEL is high or if the LDRV bit of Register 5 (DB3) is set to 1. A 1x LO or 2x LO output can be selected by setting the LDIV bit of Register 5 (DB5) to 1 or 0 respectively (see Table 7). Local Oscillator Input/Output. The internally generated 1x LO or 2x LO is available on these pins. When internal LO generation is disabled, an external 1x LO or 2x LO can be applied to these pins. VCO Control Voltage Input. This pin is driven by the output of the loop filter. Nominal input voltage range on this pin is 1.3 V to 2.5 V. If the external VCO mode is activated, this pin can be left open. Decoupling Node for VCO LDO. Connect a 100 pF capacitor and a 10 F capacitor between this pin and ground. Exposed Paddle. The exposed paddle should be soldered to a low impedance ground plane.
14
LE
16 18, 19, 32, 33 26 36
ENOP QP, QN, IN, IP RFOUT LOSEL
37, 38
LON, LOP
39
VTUNE
40
DECL3 EP
Table 6. Enabling RFOUT
ENOP X1 0 1
1
Register 5 Bit DB6 0 X1 1
RFOUT Disabled Disabled Enabled
X = don't care.
Table 7. LO Port Configuration 1, 2
LON/LOP Function
Input (2x LO) Output (Disabled) Output (1x LO) Output (1x LO) Output (1x LO) Output (2x LO) Output (2x LO) Output (2x LO)
1 2
LOSEL
0 0 0 1 1 0 1 1
Register 5 Bit DB5(LDIV)
X X 0 0 0 1 1 1
Register 5 Bit DB4(LXL)
1 0 0 0 0 0 0 0
Register 5 Bit DB3 (LDRV)
0 0 1 0 1 1 0 1
X = don't care. LOSEL should not be left floating.
Rev. 0 | Page 9 of 36
ADRF6702 TYPICAL PERFORMANCE CHARACTERISTICS
VS = 5 V; TA = 25C; baseband I/Q amplitude = 1 V p-p differential sine waves in quadrature with a 500 mV dc bias; baseband I/Q frequency (fBB) = 1 MHz; fPFD = 38.4 MHz; fREF = 153.6 MHz at +4 dBm Re:50 (1 V p-p); 130 kHz loop filter, unless otherwise noted.
10 9 TA = -40C TA = +25C TA = +85C
10 9
SSB OUTPUT POWER (dBm)
SSB OUTPUT POWER (dBm)
8 7 6 5 4 3 2 1
08568-104
8 7 6 5 4 3 2 1
08568-107
VS = 5V
VS = 5.25V
VS = 4.75V
0 1550 1600 1650 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 LO FREQUENCY (MHz)
0 1550 1600 1650 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150
LO FREQUENCY (MHz)
Figure 4. Single Sideband (SSB) Output Power (POUT) vs. LO Frequency (fLO) and Temperature; Multiple Devices Shown
20 19 1dB OUTPUT COMPRESSION (dBm) 18 17 16 15 14 13 12 11
08568-105
Figure 7. Single Sideband (SSB) Output Power (POUT) vs. LO Frequency (fLO) and Power Supply; Multiple Devices Shown
20 19 1dB OUTPUT COMPRESSION (dBm) 18 17 16 15 14 13 12 11
08568-108
TA = -40C TA = +25C TA = +85C
VS = 5V
VS = 5.25V
VS = 4.75V
10 1550 1600 1650 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 LO FREQUENCY (MHz)
10 1550 1600 1650 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 LO FREQUENCY (MHz)
Figure 5. SSB Output 1dB Compression Point (OP1dB) vs. LO Frequency (fLO) and Temperature; Multiple Devices Shown
0 -10 SSB OUTPUT POWER (dBm) CARRIER FEEDTHROUGH (dBm) THIRD-ORDER DISTORTION (dBc) 20 16
Figure 8. SSB Output 1dB Compression Point (OP1dB) vs. LO Frequency (fLO) and Power Supply
0 -10
SSB OUTPUT POWER (dBm) SIDEBAND SUPPRESSION (dBc) CARRIER FEEDTHROUGH (dBm) THIRD-ORDER DISTORTION (dBc) 20 16
SECOND-ORDER DISTORTION (dBc), THIRD-ORDER DISTORTION (dBc), CARRIER FEEDTHROUGH (dBm), SIDEBAND SUPPRESSION (dBc)
SECOND-ORDER DISTORTION (dBc), THIRD-ORDER DISTORTION (dBc), CARRIER FEEDTHROUGH (dBm), SIDEBAND SUPPRESSION (dBc)
SSB OUTPUT POWER (dBm)
-30 -40 -50 -60 -70 -80 -90
8 4 0 -4 -8 -12
-30 -40 -50 -60 -70 -80 -90
8 4 0 -4 -8
SIDEBAND SUPPRESSION (dBc)
SECOND-ORDER DISTORTION (dBc) 1 BASEBAND INPUT VOLTAGE (V p-p Differential)
SECOND-ORDER DISTORTION (dBc)
-12 -16
-16
08568-106
1 BASEBAND INPUT VOLTAGE (V p-p Differential)
Figure 6. SSB Output Power, Second- and Third-Order Distortion, Carrier Feedthrough and Sideband Suppression vs. Baseband Differential Input Voltage (fOUT = 1960 MHz)
Figure 9. SSB Output Power, Second- and Third-Order Distortion, Carrier Feedthrough and Sideband Suppression vs. Baseband Differential Input Voltage (fOUT = 2140 MHz)
Rev. 0 | Page 10 of 36
08568-109
-100 0.1
-20 10
-100 0.1
-20 10
SSB OUTPUT POWER (dBm)
-20
12
-20
12
ADRF6702
0 -10
CARRIER FEEDTHROUGH (dBm) TA = -40C TA = +25C TA = +85C CARRIER FEEDTHROUGH (dBm)
0 -10 -20 -30 -40 -50 -60 -70
TA = -40C TA = +25C TA = +85C
-20 -30 -40 -50 -60 -70 -80 1550 1600 1650 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150
LO FREQUENCY (MHz)
08568-110
LO FREQUENCY (MHz)
Figure 10. Carrier Feedthrough vs. LO Frequency (fLO) and Temperature; Multiple Devices Shown
0 -10
Figure 13. Carrier Feedthrough vs. LO Frequency (fLO) and Temperature After Nulling at 25C; Multiple Devices Shown
0 -10
SIDEBAND SUPPRESSION (dBc)
TA = -40C TA = +25C TA = +85C
TA = -40C TA = +25C TA = +85C
SIDEBAND SUPPRESSION (dBc)
-20 -30 -40 -50 -60 -70 -80
08568-111
-20 -30 -40 -50 -60 -70 -80
08568-114
08568-115
-90 1550 1600 1650 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 LO FREQUENCY (MHz)
-90 1550 1600 1650 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 LO FREQUENCY (MHz)
Figure 11. Sideband Suppression vs. LO Frequency (fLO) and Temperature; Multiple Devices Shown
90 80
OUTPUT IP3 AND IP2 (dBm)
Figure 14. Sideband Suppression vs. LO Frequency (fLO) and Temperature After Nulling at 25C; Multiple Devices Shown
-20 -25 TA = -40C TA = +25C TA = +85C
OIP2
THIRD-ORDER DISTORTION (dBc), SECOND-ORDER DISTORTION (dBc)
-30 -35 -40 -45 -50 -55 -60 -65 -70 -75 THIRD-ORDER DISTORTION
70 60 50 40 OIP3 30 20 10 TA = -40C TA = +25C TA = +85C
08568-112
0 1550 1600 1650 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 LO FREQUENCY (MHz)
SECOND-ORDER DISTORTION -80 1550 1600 1650 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 LO FREQUENCY (MHz)
Figure 12. OIP3 and OIP2 vs. LO Frequency (fLO) and Temperature (POUT -2 dBm per Tone); Multiple Devices Shown
Figure 15. Second- and Third-Order Distortion vs. LO Frequency (fLO) and Temperature
Rev. 0 | Page 11 of 36
08568-113
-80 1550 1600 1650 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150
ADRF6702
PHASE NOISE, LO FREQUENCY = 1850MHz (dBc/Hz)
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 1k 130kHz LOOP FILTER TA = -40C TA = +25C TA = +85C 1.0 0.9 INTEGRATED PHASE NOISE ( rms) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 10k 100k 1M 10M 100M
08568-116
08568-119
08568-121 08568-120
TA = -40C TA = +25C TA = +85C
2.5kHz LOOP FILTER
0 1550 1600 1650 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 LO FREQUENCY (MHz)
OFFSET FREQUENCY (Hz)
Figure 16. Phase Noise vs. Offset Frequency and Temperature, fLO = 1850 MHz
PHASE NOISE, LO FREQUENCY = 1960MHz (dBc/Hz)
0 -10 -20 -30 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 1k 130kHz LOOP FILTER -40 2.5kHz LOOP FILTER TA = -40C TA = +25C TA = +85C -80 -85 -90 -95
Figure 19. Integrated Phase Noise vs. LO Frequency
TA = -40C TA = +25C TA = +85C OFFSET = 1kHz
PHASE NOISE (dBc/Hz)
-100 -105 -110 -115 -120 -125 -130 -135 -140 -145 -150 1550 1600 1650 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 LO FREQUENCY (MHz) OFFSET = 5MHz OFFSET = 100kHz
10k
100k
1M
10M
100M
OFFSET FREQUENCY (Hz)
Figure 17. Phase Noise vs. Offset Frequency and Temperature, fLO = 1960 MHz
PHASE NOISE, LO FREQUENCY = 2140MHz (dBc/Hz)
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 10k 100k 1M 10M 100M
08568-118
08568-117
Figure 20. Phase Noise vs. LO Frequency at 1 kHz, 100 kHz, and 5 MHz Offsets
-80 -85 -90 -95 -100 -105 -110 -115 -120 -125 -130 -135 -140 -145 -150 -155 -160 1550 1600 1650 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 LO FREQUENCY (MHz) TA = -40C TA = +25C TA = +85C
TA = -40C TA = +25C TA = +85C
PHASE NOISE (dBc/Hz)
OFFSET = 10kHz
2.5kHz LOOP FILTER
OFFSET = 1MHz
130kHz LOOP FILTER
-160 1k
OFFSET FREQUENCY (Hz)
Figure 18. Phase Noise vs. Offset Frequency and Temperature, fLO = 2140 MHz
Figure 21. Phase Noise vs. LO Frequency at 10 kHz and 1 MHz Offsets
Rev. 0 | Page 12 of 36
ADRF6702
-70 -75 -80
SPUR LEVEL (dBc) SPUR LEVEL (dBc)
2 x PFD FREQUENCY 4 x PFD FREQUENCY
TA = -40C TA = +25C TA = +85C
-70 -75 -80 -85 -90 -95 -100 -105 -110 -115
08568-122
2 x PFD FREQUENCY 4 x PFD FREQUENCY
TA = -40C TA = +25C TA = +85C
-85 -90 -95 -100 -105 -110 -115 -120 1550 1600 1650 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150
LO FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 22. PLL Reference Spurs vs. LO Frequency (2x PFD and 4x PFD) at Modulator Output
-70 -75 -80 SPUR LEVEL (dBc) 1 x PFD FREQUENCY 3 x PFD FREQUENCY TA = -40C TA = +25C TA = +85C
Figure 25. PLL Reference Spurs vs. LO Frequency (2x PFD and 4x PFD) at LO Output
-70 -75 -80
SPUR LEVEL (dBc) TA = -40C TA = +25C TA = +85C
1 x PFD FREQUENCY 3 x PFD FREQUENCY
-85 -90 -95 -100 -105 -110 -115 0.5 x PFD FREQUENCY
08568-123
-85 -90 -95 -100 -105 -110 -115
08568-125
0.5 x PFD FREQUENCY
-120 1550 1600 1650 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 LO FREQUENCY (MHz)
-120 1550 1600 1650 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150
LO FREQUENCY (MHz)
Figure 23. PLL Reference Spurs vs. LO Frequency (0.5x PFD, 1x PFD, and 3x PFD) at Modulator Output
2.8 2.6 2.4
Figure 26. PLL Reference Spurs vs. LO Frequency (0.5x PFD, 1x PFD, and 3x PFD) at LO Output
0 -20 -40
TA = -40C TA = +25C TA = +85C
PHASE NOISE (dBc/Hz)
2.2
VTUNE (V)
-60 -80 -100 -120 -140 -160
LO = 1943.26MHz LO = 2140.48MHz
2.0 1.8 1.6 1.4 1.2
08568-124
LO = 1841.074MHz
10k
100k
1M
10M
LO FREQUENCY (MHz)
FREQUENCY (Hz)
Figure 24. VTUNE vs. LO Frequency and Temperature
Figure 27. Open-Loop VCO Phase Noise at 1841.074 MHz, 1943.26 MHz, and 2140.48 MHz
Rev. 0 | Page 13 of 36
08568-127
1.0 1550 1600 1650 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150
-180 1k
08568-126
-120 1550 1600 1650 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150
ADRF6702
100 90 1850MHz 1960MHz 2140MHz
2.0 1.9 1.8 1.7
CUMULATIVE PERCENTAGE (%)
80 70
VPTAT (V)
60 50 40 30 20 10
08568-128
1.6 1.5 1.4 1.3 1.2 1.1
-159
-158
-157
-156
-155
-15
10
35
60
85
NOISE FLOOR (dBm/Hz)
TEMPERATURE (C)
Figure 28. IQ Modulator Noise Floor Cumulative Distributions at 1850 MHz, 1960 MHz, and 2140 MHz
25
FREQUENCY DEVIATION FROM 1960MHz (MHz)
20 15 10 5 0 -5 -8 -10 -15 -9
08568-129
Figure 31. VPTAT Voltage vs. Temperature
0 -1 -2 RETURN LOSS (dB) -3 -4 -5 LO INPUT -6 -7 RF OUT
0
50
100
150 TIME (s)
200
250
300
LO FREQUENCY (MHz)
Figure 29. Frequency Deviation from LO Frequency at LO = 1.97 GHz to 1.96 GHz vs. Lock Time
SSB OUTPUT POWER AND LO FEEDTHROUGH (dBm)
0 -10 -20
Figure 32. Input Return Loss of LO Input (LON, LOP Driven Through MABA007159 1:1 Balun) and Output Return Loss of RFOUT vs. Frequency
280 270 260
SUPPLY CURRENT (mA)
-30 -40 -50 -60 -70 -80 -90
08568-130
250 240 230 220 210 200 190
TA = +85C
TA = +25C
SSB OUTPUT POWER
TA = -40C
LO FEEDTHROUGH
LO FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 30. SSB Output Power and LO Feedthrough with RF Output Disabled
Figure 33. Power Supply Current vs. Frequency and Temperature (PLL and IQMOD Enabled, LO Buffer Disabled)
Rev. 0 | Page 14 of 36
08568-133
-100 1550 1600 1650 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150
180 1550 1600 1650 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150
08568-032
-10 1550 1600 1650 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150
08568-131
0 -160
1.0 -40
ADRF6702 THEORY OF OPERATION
The ADRF6702 integrates a high performance IQ modulator with a state of the art fractional-N PLL. The ADRF6702 also integrates a low noise VCO. The programmable SPI port allows the user to control the fractional-N PLL functions and the modulator optimization functions. This includes the capability to operate with an externally applied LO or VCO. The quadrature modulator core within the ADRF6702 is a part of the next generation of industry-leading modulators from Analog Devices, Inc. The baseband inputs are converted to currents and then mixed to RF using high performance NPN transistors. The mixer output currents are transformed to a single-ended RF output using an integrated RF transformer balun. The high performance active mixer core, coupled with the low-loss RF transformer balun results in an exceptional OIP3 and OP1dB, with a very low output noise floor for excellent dynamic range. The use of a passive transformer balun rather than an active output stage leads to an improvement in OIP3 with no sacrifice in noise floor. At 1960 MHz the ADRF6702 typically provides an output P1dB of 13.6 dBm, OIP3 of 30.1 dBm, and an output noise floor of -156.5 dBm/Hz. Typical image rejection under these conditions is -44.4 dBc with no additional I and Q gain compensation.
BASIC CONNECTIONS FOR OPERATION
Figure 34 shows the basic connections for operating the ADRF6702 as they are implemented on the device's evaluation board. The seven power supply pins should be individually decoupled using 100 pF and 0.1 F capacitors located as close as possible to the pins. A single 10 F capacitor is also recommended. The three internal decoupling nodes (labeled DECL3, DECL2, and DECL1) should be individually decoupled with capacitors as shown in Figure 34. The four I and Q inputs should be driven with a bias level of 500 mV. These inputs are generally dc-coupled to the outputs of a dual DAC (see the DAC-to-IQ Modulator Interfacing and IQ Filtering sections for more information). A 1 V p-p (0.353 V rms) differential sine wave on the I and Q inputs results in a single sideband output power of +4.1 dBm (at 1960 MHz) at the RFOUT pin (this pin should be ac-coupled as shown in Figure 34). This corresponds to an IQ modulator voltage gain of +0.1 dB. The reference frequency for the PLL (typically 1 V p-p between 12 MHz and 160 MHz) should be applied to the REFIN pin, which should be ac-coupled. If the REFIN pin is being driven from a 50 source (for example, a lab signal generator), the pin should be terminated with 50 as shown in Figure 34 (an RF drive level of +4 dBm should be applied). Multiples or fractions of the REFIN signal can be brought back off-chip at the multiplexer output pin (MUXOUT). A lock-detect signal and an analog voltage proportional to the ambient temperature can also be brought out on this pin by setting the appropriate bits on (DB21-DB23) in Register 4 (see the Register Description section).
PLL + VCO
The fractional divide function of the PLL allows the frequency multiplication value from REFIN to the LOP/LON outputs to be a fractional value rather than restricted to an integer as in traditional PLLs. In operation, this multiplication value is INT + (FRAC/MOD) where INT is the integer value, FRAC is the fractional value, and MOD is the modulus value, all of which are programmable via the SPI port. In previous fractional-N PLL designs, the fractional multiplication was achieved by periodically changing the fractional value in a deterministic way. The downside of this was often spurious components close to the fundamental signal. In the ADRF6702, a sigma delta modulator is used to distribute the fractional value randomly, thus significantly reducing the spurious content due to the fractional function.
EXTERNAL LO
The internally generated local oscillator (LO) signal can be brought off-chip as either a 1x LO or a 2x LO (via pins LOP and LON) by asserting the LOSEL pin and making the appropriate internal register settings. The LO output must be disabled whenever the RF output of the IQ modulator is disabled. The LOP and LON pins can also be used to apply an external LO. This can be used to bypass the internal PLL/VCO or if operation using an external VCO is desired. To turn off the PLL Register 6, Bits[20:17] must be zero.
Rev. 0 | Page 15 of 36
ADRF6702
VCC VCC RED +5V R43 10k (0402) R20 0 (0402)
C28 10F (3216)
C7 0.1F (0402) C8 100pF (0402) C27 0.1F (0402) C26 100pF (0402) VDD
29 27
S2
R47 10k (0402) C9 0.1F (0402) C10 100pF (0402)
VCC R39 10k (0402) S1 VDD R40 10k (0402) EXT LO 5 4
T3 34
C25 0.1F (0402) C24 100pF (0402) VDD
22
C23 0.1F (0402) C22 100pF (0402) VDD
17
C20 0.1F (0402) C21 100pF (0402) VDD
10
C19 0.1F (0402) C18 100pF (0402) VDD
1
LE (USB) DATA (USB) CLK (USB)
ENOP DATA CLK
13
VDD
16
12
LE
14 9
DECL2 C16 100pF (0402) DECL1 C12 100pF (0402) C17 0.1F (0402) C11 0.1F (0402) C42 10F (0603) C41 OPEN (0603)
LOSEL LON 1 3
36 37 BUFFER
C6 100pF LOP 38 (0402) FRACTION REG MODULUS INTEGER REG
DIVIDER /2 2:1 MUX
SPI INTERFACE
2
BUFFER
MABA-007159 C5 100pF (0402) C29 100pF (0402)
ADRF6702
x2
6
REF_IN R73 49.9 (0402) SEE TEXT REFOUT OPEN
REFIN
THIRD-ORDER FRACTIONAL INTERPOLATOR MUX TEMP SENSOR
4 7
18
QP R23 OPEN (0402)
QP
N COUNTER 21 TO 123
PRESCALER /2 CHARGE PUM P 250A, 500A (DEFAULT), 750A, 1000A
24 5 3
VCO CORE /2 0/90
19
QN IN
QN IN
/2 /4 MUXOUT
8
- PHASE + FREQUENCY DETECTOR
32
R16 OPEN (0402)
11 15 20 21 23 25 28 30 31 35
39
40
26
33
IP
R3 OPEN (0402)
IP
NC GND CP TEST POINT (OPEN) R38 OPEN (0402) C14 22pF (0603)
R2 R37 OPEN 0 (0402) (0402)
RSET
CP
VTUNE R62 0 (0402)
DECL3
RFOUT OPEN
R9 10k R65 10k (0402) (0402) R10 3k (0603) C15 2.7nF (1206) R11 OPEN (0402) C13 6.8pF (0603) C40 22pF (0603) R12 0 (0402) C1 100pF (0402) R63 OPEN (0402)
VTUNE OPEN
C3 100pF (0402)
RFOUT
NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
Figure 34. Basic Connections for Operation (Loop Filter Set to 130 kHz)
LOOP FILTER
The loop filter is connected between the CP and VTUNE pins. The return for the loop filter components should be to Pin 40 (DECL3). The loop filter design in Figure 34 results in a 3 dB loop bandwidth of 130 kHz. The ADRF6702 closed loop phase noise was also characterized using a 2.5 kHz loop filter design. The recommended components for both filter designs are shown in Table 8. For assistance in designing loop filters with other characteristics, download the most recent revision of ADIsimPLLTM from www.analog.com/adisimpll. Operation with an external VCO is possible. In this case, the return for the loop filter components is ground (assuming a ground reference on the external VCO tuning input). The output of the loop filter is connected to the external VCO's tuning pin. The output of the VCO is brought back into the device on the LOP and LON pins (using a balun if necessary).
Table 8. Recommended Loop Filter Components
Component C14 R10 C15 R9 C13 R65 C40 R37 R11 R12 130 kHz Loop Filter 22 pF 3 k 2.7 nF 10 k 6.8 pF 10 k 22 pF 0 Open 0 2.5 kHz Loop Filter 0.1 F 68 4.7 F 270 47 nF 0 Open 0 Open 0
Rev. 0 | Page 16 of 36
08568-023
C43 10F (0603)
C2 OPEN (0402)
ADRF6702
DAC-TO-IQ MODULATOR INTERFACING
The ADRF6702 is designed to interface with minimal components to members of the Analog Devices, Inc., family of TxDACs(R). These dual-channel differential current output DACs provide an output current swing from 0 mA to 20 mA. The interface described in this section can be used with any DAC that has a similar output. An example of an interface using the AD9122 TxDAC is shown in Figure 35. The baseband inputs of the ADRF6702 require a dc bias of 500 mV. The average output current on each of the outputs of the AD9122 is 10 mA. Therefore, a single 50 resistor to ground from each of the DAC outputs results in an average current of 10 mA flowing through each of the resistors, thus producing the desired 500 mV dc bias for the inputs to the ADRF6702.
AD9122
OUT1_P RBIP 50 RBIN 50 OUT1_N IP
AD9122
OUT1_P RBIP 50 RBIN 50 OUT1_N
(SEE TEXT)
ADRF6702
IP RSL
IN
OUT2_N RBQN 50 RBQP 50 RSL (SEE TEXT)
QN
OUT2_P
QP
Figure 36. AC Voltage Swing Reduction Through the Introduction of a Shunt Resistor Between the Differential Pair
ADRF6702
IN
OUT2_N RBQN 50 RBQP 50
QN
The value of this ac voltage swing limiting resistor(RSL as shown in Figure 36) is chosen based on the desired ac voltage swing and IQ modulator output power. Figure 37 shows the relationship between the swing-limiting resistor and the peak-to-peak ac swing that it produces when 50 bias-setting resistors are used. A higher value of swing-limiting resistor will increase the output power of the ADRF6702 and signal-to-noise ratio (SNR) at the cost if higher intermodulation distortion. For most applications, the optimum value for this resistor will be between 100 and 300 . When setting the size of the swing-limiting resistor, the input impedance of the I and Q inputs should be taken into account. The I and Q inputs have a differential input resistance of 920 . As a result, the effective value of the swing-limiting resistance is 920 in parallel with the chosen swing-limiting resistor. For example, if a swing-limiting resistance of 200 is desired (based on Figure 36), the value of RSL should be set such that 200 = (920 x RSL)/(920 + RSL) resulting in a value for RSL of 255 .
2.0 1.8
OUT2_P
QP
Figure 35. Interface Between the AD9122 and ADRF6702 with 50 Resistors to Ground to Establish the 500 mV DC Bias for the ADRF6702 Baseband Inputs
The AD9122 output currents have a swing that ranges from 0 mA to 20 mA. With the 50 resistors in place, the ac voltage swing going into the ADRF6702 baseband inputs ranges from 0 V to 1 V (with the DAC running at 0 dBFS). So the resulting drive signal from each differential pair is 2 V p-p differential with a 500 mV dc bias.
ADDING A SWING-LIMITING RESISTOR
The voltage swing for a given DAC output current can be reduced by adding a third resistor to the interface. This resistor is placed in the shunt across each differential pair, as shown in Figure 36. It has the effect of reducing the ac swing without changing the dc bias already established by the 50 resistors.
DIFFERENTIAL SWING (V p-p)
08568-033
1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 100 RSL () 1000 10000
08568-035
0 10
Figure 37. Relationship Between the AC Swing-Limiting Resistor and the Peak-to-Peak Voltage Swing with 50 Bias-Setting Resistors
Rev. 0 | Page 17 of 36
08568-034
ADRF6702
IQ FILTERING
An antialiasing filter must be placed between the DAC and modulator to filter out Nyquist images and broadband DAC noise. The interface for setting up the biasing and ac swing discussed in the Adding a Swing-Limiting Resistor section, lends itself well to the introduction of such a filter. The filter can be inserted between the dc bias setting resistors and the ac swing-limiting resistor. Doing so establishes the input and output impedances for the filter. Unless a swing-limiting resistor of 100 is chosen, the filter must be designed to support different source and load impedances. In addition, the differential input capacitance of the I and Q inputs (1 pF) should be factored into the filter design. Modern filter design tools allow for the simulation and design of filters with differing source and load impedances as well as inclusion of reactive load components.
DEVICE PROGRAMMING AND REGISTER SEQUENCING
The device is programmed via a 3-pin SPI port. The timing requirements for the SPI port are shown in Table 3 and Figure 2. Eight programmable registers, each with 24 bits, control the operation of the device. The register functions are listed in Table 9. The eight registers should initially be programmed in reverse order, starting with Register 7 and finishing with Register 0. Once all eight registers have been initially programmed, any of the registers can be updated without any attention to sequencing. Software is available on the ADRF6702 product page at www.analog.com that allows programming of the evaluation board from a PC running Windows(R) XP or Windows Vista. To operate correctly under Windows XP, Version 3.5 of Microsoft .NET must be installed. To run the software on a Windows 7 PC, XP emulation mode must be used (using Virtual PC).
BASEBAND BANDWIDTH
Figure 38 shows the frequency response of the ADRF6702's baseband inputs. This plot shows 0.5 dB and 3 dB bandwidths of 350 MHz and 750 MHz respectively. Any flatness variations across frequency at the ADRF6702 RF output have been calibrated out of this measurement.
4
BASEBAND FREQUENCY RESPONSE (dBc)
2 0 -2 -4 -6 -8 -10 10
100 BB FREQUENCY (MHz)
1000
Figure 38. Baseband Bandwidth
08568-134
Rev. 0 | Page 18 of 36
ADRF6702 REGISTER SUMMARY
Table 9. Register Functions
Register Register 0 Register 1 Register 2 Register 3 Register 4 Register 5 Register 6 Register 7 Function Integer divide control (for the PLL) Modulus divide control (for the PLL) Fractional divide control (for the PLL) - modulator dither control PLL charge pump, PFD, and reference path control LO path and modulator control VCO control and VCO enable External VCO enable
Rev. 0 | Page 19 of 36
ADRF6702 REGISTER DESCRIPTION
REGISTER 0--INTEGER DIVIDE CONTROL (DEFAULT: 0x0001C0)
With Register 0, Bits[2:0] set to 000, the on-chip integer divide control register is programmed as shown in Figure 39.
Integer Divide Ratio
The integer divide ratio bits are used to set the integer value in Equation 2. The INT, FRAC, and MOD values make it possible to generate output frequencies that are spaced by fractions of the PFD frequency. The VCO frequency (fVCO) equation is fVCO = 2 x fPFD x (INT + (FRAC/MOD)) (2) where: INT is the preset integer divide ratio value (24 to 119 in fractional mode). MOD is the preset fractional modulus (1 to 2047). FRAC is the preset fractional divider ratio value (0 to MOD - 1).
Divide Mode
Divide mode determines whether fractional mode or integer mode is used. In integer mode, the RF VCO output frequency (fVCO) is calculated by fVCO = 2 x fPFD x (INT) (1) where: fVCO is the output frequency of the internal VCO. fPFD is the frequency of operation of the phase-frequency detector. INT is the integer divide ratio value (21 to 123 in integer mode).
RESERVED DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 0 0 0 0 0 0 0 0 0 0 0 0 0
DIVIDE MODE DB10 DM DB9 ID6
INTEGER DIVIDE RATIO DB8 ID5 DB7 ID4 DB6 ID3 DB5 ID2 DB4 ID1 DB3 ID0
CONTROL BITS DB2 DB1 DB0
C3(0) C2(0) C1(0)
DM 0 1
DIVIDE MODE FRACTIONAL (DEFAULT) INTEGER
ID6 0 0 0 0 ... ... 0 ... ... 1 1 1 1 1
ID5 0 0 0 0 ... ... 1 ... ... 1 1 1 1 1
ID4 1 1 1 1 ... ... 1 ... ... 1 1 1 1 1
ID3 0 0 0 1 ... ... 1 ... ... 0 1 1 1 1
ID2 1 1 1 0 ... ... 0 ... ... 1 0 0 0 0
ID1 0 1 1 0 ... ... 0 ... ... 1 0 0 1 1
ID0 1 0 1 0 ... ... 0 ... ... 1 0 1 0 1
INTEGER DIVIDE RATIO 21 (INTEGER MODE ONLY) 22 (INTEGER MODE ONLY) 23 (INTEGER MODE ONLY) 24 ... ... 56 (DEFAULT) ... ... 119 120 (INTEGER MODE ONLY) 121 (INTEGER MODE ONLY)
08568-014
122 (INTEGER MODE ONLY) 123 (INTEGER MODE ONLY)
Figure 39. Register 0--Integer Divide Control Register Map
Rev. 0 | Page 20 of 36
ADRF6702
REGISTER 1--MODULUS DIVIDE CONTROL (DEFAULT: 0x003001)
With Register 1, Bits[2:0] set to 001, the on-chip modulus divide control register is programmed as shown in Figure 40.
REGISTER 2--FRACTIONAL DIVIDE CONTROL (DEFAULT: 0x001802)
With Register 2, Bits[2:0] set to 010, the on-chip fractional divide control register is programmed as shown in Figure 41.
Modulus Value
The modulus value is the preset fractional modulus ranging from 1 to 2047.
RESERVED DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 0 0 0 0 0 0 0 0 0 0 MD10
Fractional Value
The FRAC value is the preset fractional modulus ranging from 0 to MODULUS VALUE DB12 DB11 DB10 MD9 MD8 MD7 DB9 MD6 DB8 MD5 DB7 MD4 DB6 MD3 DB5 MD2 DB4 MD1 DB3 MD0 CONTROL BITS DB2 DB1 DB0 C3(0) C2(0) C1(1)
MD10 0 0 ... ... 1 ... ... 1
MD9 0 0 ... ... 1 ... ... 1
MD8 0 0 ... ... 0 ... ... 1
MD7 0 0 ... ... 0 ... ... 1
MD6 0 0 ... ... 0 ... ... 1
MD5 0 0 ... ... 0 ... ... 1
MD4 0 0 ... ... 0 ... ... 1
MD3 0 0 ... ... 0 ... ... 1
MD2 0 0 ... ... 0 ... ... 1
MD1 0 1 ... ... 0 ... ... 1
MD0 1 0 ... ... 0 ... ... 1
MODULUS VALUE 1 2 ... ... 1536 (DEFAULT) ... ... 2047
08568-015
Figure 40. Register 1--Modulus Divide Control Register Map
RESERVED DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 0 0 0 0 0 0 0 0 0 0 FD10 DB12 DB11 DB10 FD9 FD8 FD7
FRACTIONAL VALUE DB9 FD6 DB8 FD5 DB7 FD4 DB6 FD3 DB5 FD2 DB4 FD1 DB3 FD0
CONTROL BITS DB2 DB1 DB0 C3(0) C2(1) C1(0)
FD10 0 0 ... ... 0 ... ...
FD9 0 0 ... ... 1 ... ...
FD8 0 0 ... ... 1 ... ...
FD7 0 0 ... ... 0 ... ...
FD6 0 0 ... ... 0 ... ...
FD5 0 0 ... ... 0 ... ...
FD4 0 0 ... ... 0 ... ...
FD3 0 0 ... ... 0 ... ...
FD2 0 0 ... ... 0 ... ...
FD1 0 0 ... ... 0 ... ...
FD0 0 1 ... ... 0 ... ...
FRACTIONAL VALUE 0 1 ... ... 768 (DEFAULT) ... ... 08568-016
FRACTIONAL VALUE MUST BE LESS THAN MODULUS.
Figure 41. Register 2--Fractional Divide Control Register Map
Rev. 0 | Page 21 of 36
ADRF6702
REGISTER 3--- MODULATOR DITHER CONTROL (DEFAULT: 0x10000B)
With Register 3, Bits[2:0] set to 011, the on-chip - modulator dither control register is programmed as shown in Figure 42. The recommended and default setting for dither enable is enabled (1).
DITHER MAGNITUDE DB22 DB21 DITH1 DITH0
The default value of the dither magnitude (15) should be set to a recommended value of 1. The dither restart value can be programmed from 0 to 217 - 1, though a value of 1 is typically recommended.
DB23 0
DITHER DITHER RESTART VALUE CONTROL BITS ENABLE DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DEN DV16 DV15 DV14 DV13 DV12 DV11 DV10 DV9 DV8 DV7 DV6 DV5 DV4 DV3 DV2 DV1 DV0 C3(0) C2(1) C1(1)
DITH1 0 0 1 1
DITH0 0 1 0 1
DITHER MAGNITUDE 15 (DEFAULT) 7 3 1 (RECOMMENDED) DEN 0 1 DITHER ENABLE DISABLE ENABLE (DEFAULT, RECOMMENDED) DITHER RESTART VALUE 0x00001 (DEFAULT) ... ... 0x1FFFF
DV16 DV15 DV14 DV13 0 ... ... 1 0 ... ... 1 0 ... ... 1 0 ... ... 1
DV12 0 ... ... 1
DV11 0 ... ... 1
DV10 0 ... ... 1
DV9 0 ... ... 1
DV8 DV7 0 ... ... 1 0 ... ... 1
DV6 DV5 0 ... ... 1 0 ... ... 1
DV4 0 ... ... 1
DV3 DV2 DV1 DV0 0 ... ... 1 0 ... ... 1 0 ... ... 1 1 ... ... 1
Figure 42. Register 3--- Modulator Dither Control Register Map
Rev. 0 | Page 22 of 36
08568-017
ADRF6702
REGISTER 4--PLL CHARGE PUMP, PFD, AND REFERENCE PATH CONTROL (DEFAULT: 0x0AA7E4)
With Register 4, Bits[2:0] set to 100, the on-chip charge pump, PFD, and reference path control register is programmed as shown in Figure 43. fractional spurs. The magnitude of the phase offset is determined by the following equation:
(deg) = 22.5
PFD ,OFS I CP , MULT
(4)
CP Current
The nominal charge pump current can be set to 250 A, 500 A, 750 A, or 1000 A using DB10 and DB11 of Register 4 and by setting DB18 to 0 (CP reference source). In this mode, no external RSET is required. If DB18 is set to 1, the four nominal charge pump currents (INOMINAL) can be externally tweaked according to the following equation:
217.4 x I CP R SET = I NOMINAL - 37.8
The default value of the phase offset multiplier (10 x 22.5) should be set to a recommended value of 6 x 22.5. This phase offset can be either positive or negative depending on the value of DB17 in Register 4. The reference frequency applied to the PFD can be manipulated using the internal reference path source. The external reference frequency applied can be internally scaled in frequency by 2x, 1x, 0.5x, or 0.25x. This allows a broader range of reference frequency selections while keeping the reference frequency applied to the PFD within an acceptable range. The device also has a MUXOUT pin that can be programmed to output a selection of several internal signals. The default mode is to provide a lock-detect output to allow the user to verify when the PLL has locked to the target frequency. In addition, several other internal signals can be passed to the MUXOUT pin as described in Figure 34.
(3)
where ICP is the base charge pump current in microamps. The PFD phase offset multiplier (PFD,OFS), which is set by Bits[16:12] of Register 4, causes the PLL to lock with a nominally fixed phase offset between the PFD reference signal and the divided-down VCO signal. This phase offset is used to linearize the PFD-to-CP transfer function and can improve
Rev. 0 | Page 23 of 36
ADRF6702
REF OUPUT MUX SELECT DB23 DB22 INPUT REF CURRENT REF PATH
SOURCE CP
CP SOURCE
PFD POL
PFD PHASE OFFSET MULTIPLIER
CP CURRENT
CP CONTROL DB8 DB7
PFD EDGE DB6 PE1 DB5 PE0
PFD ANTIBACKLASH DELAY DB4 DB3
CONTROL BITS DB2 DB1 C2(0) DB0 C1(0)
DB21 DB20 DB19 RS0
DB18 CPM
DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
RMS2 RMS1 RMS0 RS1
CPBD CPB4 CPB3 CPB2 CPB1 CPB0 CPP1 CPP0 CPS CPC1 CPC0
PAB1 PAB0 C3(1)
PAB1 PAB0 PFD ANTIBACKLASH DELAY 0 1 0 1 PE0 0 1 PE1 0 1 0 0 1 1 0ns (DEFAULT) 0.5ns 0.75ns 0.9ns
REFERENCE PATH EDGE SENSITIVITY FALLING EDGE RISING EDGE (DEFAULT)
DIVIDER PATH EDGE SENSITIVITY FALLING EDGE RISING EDGE (DEFAULT)
CPC1 CPC0 CHARGE PUMP CONTROL 0 0 1 1 CPS 0 1 0 1 0 1 BOTH ON PUMP DOWN PUMP UP TRISTATE (DEFAULT)
CHARGE PUMP CONTROL SOURCE CONTROL BASED ON STATE OF DB7/DB8 (CP CONTROL) CONTROL FROM PFD (DEFAULT)
CPP1 CPP0 CHARGE PUMP CURRENT 0 0 1 1 0 1 0 1 250A 500A (DEFAULT) 750A 1000A
CPB4 CPB3 CPB2 CPB1 CPB0 PFD PHASE OFFSET MULTIPLIER 0 0 0 0 1 1 CPBD 0 1 CPM 0 1 RS1 0 1 0 1 0 0 0 1 0 1 0 0 1 0 0 1 0 0 1 1 0 1 0 1 0 0 0 1 0 x 22.5/ICP,MULT 1 x 22.5/ICP,MULT 6 x 22.5/ICP,MULT (RECOMMENDED) 10 x 22.5/ICP,MULT (DEFAULT) 16 x 22.5/ICP,MULT 31 x 22.5/ICP,MULT
PFD PHASE OFFSET POLARITY NEGATIVE POSITIVE (DEFAULT)
CHARGE PUMP CURRENT REFERENCE SOURCE INTERNAL (DEFAULT) EXTERNAL
INPUT REF RS0 PATH SOURCE 0 0 1 1 2x REFIN REFIN (DEFAULT) 0.5x REFIN 0.25x REFIN
RMS2 RMS1 RMS0 REF OUTPUT MUX SELECT 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 LOCK DETECT (DEFAULT) VPTAT REFIN (BUFFERED) 0.5x REFIN (BUFFERED) 2x REFIN (BUFFERED) TRISTATE RESERVED RESERVED
Figure 43. Register 4--PLL Charge Pump, PFD, and Reference Path Control Register Map
Rev. 0 | Page 24 of 36
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ADRF6702
REGISTER 5--LO PATH AND MODULATOR CONTROL (DEFAULT: 0X0000D5)
With Register 5, Bits[2:0] set to 101, the LO path and modulator control register is programmed as shown in Figure 44. The modulator output or the complete modulator can be disabled using the modulator bias enable and modulator output enable addresses of Register 5. The LO port (LOP and LON pins) can be used to apply an external 2x LO (that is, bypass internal PLL) to the IQ modulator. A differential LO drive of 0 dBm is recommended. The LO port can also be used as an output where a 2x LO or 1x LO can be brought out and used to drive another mixer. The nominial output power provided at the LO port is 3 dBm. The mode of operation of the LO port is determined by the status of the LOSEL pin (3.3 V logic) along with the settings in a number of internal registers (see Table 10).
Table 10. LO Port Configuration1, 2
LON/LOP Function Input (2x LO) Output (Disabled) Output (1x LO) Output (1x LO) Output (1x LO) Output (2x LO) Output (2x LO) Output (2x LO)
1 2
LOSEL 0 0 0 1 1 0 1 1
Register 5, Bit DB5 (LDIV) X X 0 0 0 1 1 1
Register 5, Bit DB4 (LXL) 1 0 0 0 0 0 0 0
Register 5, Bit DB3 (LDRV) 0 0 1 0 1 1 0 1
X = don't care. LOSEL should not be left floating.
The internal VCO of the device can also be bypassed. In this case, the charge pump output drives an external VCO through the loop filter. The loop is completed by routing the VCO into the device through the LO port.
LO OUTPUT MOD RF LO LO BIAS OUTPUT OUTPUT IN/OUT DRIVER CONTROL BITS RESERVED ENABLE ENABLE DIVIDER CONTROL ENABLE DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MBE RFEN LDIV LXL LDRV C3(1) C2(0) C1(1)
LO OUTPUT DRIVER LDRV ENABLE 0 1 LXL 0 1 LDIV 0 1 RFEN 0 1 MBE 0 1 DRIVER OFF (DEFAULT) DRIVER ON
LO INPUT/OUTPUT CONTROL LO OUTPUT (DEFAULT) LO INPUT
LO OUTPUT DIVIDE MODE DIVIDE BY 1 DIVIDE BY 2 (DEFAULT)
RF OUTPUT ENABLE DISABLE ENABLE (DEFAULT)
MOD BIAS ENABLE DISABLE ENABLE (DEFAULT)
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Figure 44. Register 5--LO Path and Modulator Control Register Map
Rev. 0 | Page 25 of 36
ADRF6702
REGISTER 6--VCO CONTROL AND VCO ENABLE (DEFAULT: 0X1E2106)
With Register 6, Bits[2:0] set to 110, the VCO control and enable register is programmed as shown in Figure 45. The VCO tuning band is normally selected automatically by the band calibration algorithm, although the user can directly select the VCO band using Register 6. The VCO BS SRC bit (DB9) determines whether the result of the calibration algorithm is used to select the VCO band or if the band selected is based on the value in VCO band select (DB8 to DB3). The VCO amplitude can be controlled through Register 6. The VCO amplitude setting can be controlled between 0 and 63. The default value of 8 should be set to a recommended value of 63. The internal VCOs can be disabled using Register 6. The internal charge pump can be disabled through Register 6. By default, the charge pump is enabled. To turn off the PLL (for example, if the ADRF6702 is being driven by an external LO), set Register 6, Bits[20:17] to zero.
REGISTER 7--EXTERNAL VCO ENABLE
With Register 7, Bits[2:0] set to 111, the external VCO control register is programmed as shown in Figure 46. The external VCO enable bit allows the use of an external VCO in the PLL instead of the internal VCO. This can be advantageous in cases where the internal VCO is not capable of providing the desired frequency or where the internal VCO's phase noise is higher than desired. By setting this bit (DB22) to 1, and setting Register 6, Bits[15:10] to 0, the internal VCO is disabled, and the output of an external VCO can be fed into the part differentially on Pin 38 and Pin 37 (LOP and LON). Because the loop filter is already external, the output of the loop filter simply needs to be connected to the external VCO's tuning voltage pin.
RESERVED DB23 DB22 DB21 0 0 0
3.3V CHARGE VCO LDO VCO VCO PUMP LDO ENABLE ENABLE ENABLE ENABLE SWITCH DB20 CPEN DB19 L3EN DB18 LVEN
VCO AMPLITUDE
VCO BW SW CTRL
VCO BAND SELECT FROM SPI
CONTROL BITS
DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 VCO EN VCO SW VC5 VC4 VC3 VC2 VC1 VC0 VBSRC VBS5 VBS4 VBS3 VBS2 VBS1 VBS0 C3(1) C2(1) C1(0) VC[5:0] VCO AMPLITUDE 0x00 .... 0x18 .... 0x2B .... 0x3F VCO SW 0 1 VCO EN 0 1 0 .... 8 (DEFAULT) .... 43 .... 63 (RECOMMENDED) VBS[5:0] 0x00 0x01 .... 0x3F VCO BAND SELECT FROM SPI DEFAULT 0x20
CPEN CHARGE PUMP ENABLE 0 1 DISABLE ENABLE (DEFAULT) L3EN 3.3V LDO ENABLE 0 1 DISABLE ENABLE (DEFAULT) LVEN 0 1 VCO LDO ENABLE DISABLE ENABLE (DEFAULT)
VBSRC VCO BW CAL AND SW SOURCE CONTROL 0 1 BAND CAL (DEFAULT) SPI
VCO SWITCH CONTROL FROM SPI REGULAR (DEFAULT) BAND CAL
VCO ENABLE DISABLE ENABLE (DEFAULT)
08568-020
Figure 45. Register 6--VCO Control and VCO Enable Register Map
EXTERNAL VCO RESERVED ENABLE DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 0 XVCO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RES XVCO 0 1 EXTERNAL VCO ENABLE INTERNAL VCO (DEFAULT) EXTERNAL VCO
CONTROL BITS DB7 DB6 DB5 0 0 0 DB4 DB3 DB2 DB1 DB0 0 0 C3(1) C2(1) C1(1)
Figure 46. Register 7--External VCO Enable Register Map
Rev. 0 | Page 26 of 36
08568-021
ADRF6702 CHARACTERIZATION SETUPS
Figure 47 and Figure 48 show characterization bench setups used to characterize the ADRF6702. The setup shown in Figure 47 was used to do most of the testing. An automated VEE program was used to control equipment over the IEEE bus. The setup was used to measure SSB, OIP2, OIP3, OP1dB, LO, and USB NULL. For phase noise and reference spurs measurements, see the phase noise setup on Figure 48. Phase noise was measured on LO and modulator output.
ADRF670x TEST RACK ASSEMBLY (INTERNAL VCO CONFIGURATION) ALL INSTRUMENTS ARE CONNECTED IN DAISY CHAIN FASHION VIA GBIP CABLE UNLESS OTHERWISE NOTED.
E3631A POWER SUPPLY (+6V ADJUSTED TO 5V)
+5V FOR VPOS TO 34950 MODULE
34401A DMM (FOR SUPPLY CURRENT MEASUREMENT)
34980A WITH 34950 AND (x2) 34921 MODULES
PROGRAMMING AND DC CABLE (x6 FOR MULTISITE)
INPUT (RFOUT) AGILENT E4440A PSA SPECTRUM ANALYZER 10-PIN CONNECTOR DC HEADER REF IN KEITHLEY S46 SWITCH SYSTEM #1 (FOR RFOUT AND REFIN ON 6 SITES) OUTPUT (REF) KEITHLEY S46 SWITCH SYSTEM #2 (FOR BASEBAND INPUTS ON 6 SITES)
6dB
9-PIN DSUB CONNECTOR (REGISTER PROGRAMMING)
RF OUT
6dB
ADRF6702 EVAL BOARD
ROHDE AND SCHWARTZ SMT 06 SIGNAL GENERATOR (REFIN) BASEBAND INPUTS AT 1MHz
BASEBAND OUTPUTS (IN, IP, QN, QP)
08568-043
AEROFLEX IFR 3416 FREQUENCY GENERATOR (WITH BASEBAND OUTPUTS AT 1MHz) PC CONTROL CONNECTED TO SYSTEM VIA USB TO GPIB ADAPTER
Figure 47. General Characterization Setup
Rev. 0 | Page 27 of 36
ADRF6702
ADRF670x PHASE NOISE STAND SETUP ALL INSTRUMENTS ARE CONNECTED IN DAISY CHAIN FASHION VIA GBIP CABLE UNLESS OTHERWISE NOTED.
ROHDE AND SCHWARTZ SMA 100 SIGNAL GENERATOR REFIN AGILENT E5052 SIGNAL SOURCE ANALYZER AGILENT E4440A SPECTRUM ANALYZER
IF OUT
KEITHLEY S46 SWITCH SYSTEM 2 (FOR IF OUT AND REFIN ON 6 SITES)
REFIN
LO OUT
BASEBAND INPUTS (IP, IN, QP, QN) IFR 3416 SIGNAL GENERATOR (BASEBAND SOURCE) KEITHLEY S46 SWITCH SYSTEM 1 (FOR BASEBAND INPUTS ON 6 SITES)
10 PIN CONNECTOR (DC MEASUREMENT, +5V POS) AND 9 PIN DSUB CONNECTOR (VCO AND PLL PROGRAMMING)
ADRF6702 EVAL BOARD
34980A MULTIFUNCTION SWITCH (WITH 34950 AND 34921 MODULES)
AGILENT E3631A POWER SUPPLY
INPUT DC
Figure 48. Characterization Setup for Phase Noise and Reference Spur Measurements
Rev. 0 | Page 28 of 36
08568-044
AGILENT 34401A DMM (IN DC I MODE, SUPPLY CURRENT MEASUREMENT)
PC CONTROL CONNECTED TO SYSTEM VIA USB TO GPIB ADAPTER
ADRF6702 EVALUATION BOARD
Figure 50 shows the schematic of the device's RoHS-compliant evaluation board. This board was designed using Rogers 4350 material to minimize losses at high frequencies. FR4 material would also be adequate but with the slightly higher trace loss of this material. Whereas the on-board USB interface circuitry of the evaluation board is powered directly from the PC, the main section of the evaluation board requires a separate 5 V power supply. The evaluation board is designed to operate using the internal VCO (default configuration) of the device or with an external VCO. To use an external VCO, R62 and R12 should be removed. 0 resistors should be placed in R63 and R11. A side-launched SMA connector (Johnson 142-0701-851) must be soldered to the pad labeled VTUNE. The input of the external VCO should be connected to the VTUNE SMA connector and a portion of the VCO's output should be connected to the EXT LO SMA connector. In addition to these hardware changes, internal register settings must also be changed (as detailed in the Register Description section) to enable operation with an external VCO. Additional configuration options for the evaluation board are described in Table 11. The serial port of the ADRF6702 can be programmed from a PC's USB port (a USB cable is provided with the evaluation board). The on-board USB interface circuitry can if desired be bypassed by removing the 0 resistors, R15, R17, and R18 (see Figure 50) and driving the ADRF6702 serial interface through the P3 4-pin header (P3 must be first installed, Samtec TSW104-08-G-S).
08568-135
To operate correctly under Windows XP, Version 3.5 of Microsoft .NET must be installed. To run the software on a Windows 7 PC, XP emulation mode must be used (using Virtual PC).
Figure 49. Control Software Opening Menu
EVALUATION BOARD CONTROL SOFTWARE
USB-based programming software is available to download from the ADRF6702 product page at www.analog.com (Evaluation Board Software Rev 6.1.0). To install the software, download and extract the zip file. Then run the following installation file: ADRF6X0X_6p1p0_customer_installer.exe.
Figure 49 shows the opening window of the software where the user selects the device being programmed. Figure 53 shows a screen shot of the control software's main controls with the default settings displayed. The text box in the bottom left corner provides an immediate indication of whether the software is successfully communicating with the evaluation board. If the evaluation board is connected to the PC via the USB cable provided and the software is successfully communicating with the on-board USB circuitry, this text box shows the following message: ADRF6X0X eval board connected.
Rev. 0 | Page 29 of 36
ADRF6702
VCC VCC RED +5V R43 10k (0402) C28 10F (3216) S2 R20 0 (0402)
R47 10k (0402) C9 0.1F (0402) C10 100pF (0402)
VCC R39 10k (0402) S1 VDD R40 10k (0402) 5 4
T3 34
C7 0.1F (0402) C8 100pF (0402) VDD
29
C27 0.1F (0402) C26 100pF (0402) VDD
27
C25 0.1F (0402) C24 100pF (0402) VDD
22
C23 0.1F (0402) C22 100pF (0402) VDD
17
C20 0.1F (0402) C21 100pF (0402) VDD
10
C19 0.1F (0402) C18 100pF (0402) VDD
1
LE (USB) DATA (USB) CLK (USB)
ENOP DATA CLK
13
16
12
LE
14 9
DECL2 C16 100pF (0402) DECL1 C12 100pF (0402) C17 0.1F (0402) C11 0.1F (0402) C42 10F (0603) C41 OPEN (0603)
LOSEL LON
36 37 BUFFER
EXT LO
1 3
C6 100pF LOP 38 (0402) FRACTION REG MODULUS INTEGER REG
DIVIDER /2 2:1 MUX
SPI INTERFACE
2
BUFFER
MABA-007159 C5 100pF (0402) C29 100pF (0402)
ADRF6702
x2
6
REF_IN R73 49.9 (0402) SEE TEXT REFOUT OPEN
REFIN
THIRD-ORDER FRACTIONAL INTERPOLATOR MUX TEMP SENSOR
4 7
18
QP R23 OPEN (0402)
QP
N COUNTER 21 TO 123
PRESCALER /2 CHARGE PUM P 250A, 500A (DEFAULT), 750A, 1000A
24 5 3
VCO CORE /2 0/90
19
QN IN
QN IN
/2 /4 MUXOUT
8
- PHASE + FREQUENCY DETECTOR
32
R16 OPEN (0402)
11 15 20 21 23 25 28 30 31 35
39
40
26
33
IP
R3 OPEN (0402)
IP
NC GND CP TEST POINT (OPEN) R38 OPEN (0402) C14 22pF (0603)
R2 R37 OPEN 0 (0402) (0402)
RSET
CP
VTUNE R62 0 (0402)
DECL3
RFOUT OPEN
R9 10k R65 10k (0402) (0402) R10 3k (0603) C15 2.7nF (1206) R11 OPEN (0402) C13 6.8pF (0603) C40 22pF (0603) R12 0 (0402) C1 100pF (0402) R63 OPEN (0402)
VTUNE OPEN
C3 100pF (0402)
RFOUT
NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
Figure 50. Evaluation Board Schematic (Loop Filter Set to 130 kHz)
08568-027
C43 10F (0603)
C2 OPEN (0402)
08568-047
Figure 52. Evaluation Board Bottom Layer Figure 51. Evaluation Board Top Layer
Rev. 0 | Page 30 of 36
08568-048
ADRF6702
Table 11. Evaluation Board Configuration Options
Component S1, R39, R40 Description LO select. Switch and resistors to ground LOSEL pin. The LOSEL pin setting in combination with internal register settings, determines whether the LOP/LON pins function as inputs or outputs. With the LOSEL pin grounded, register settings can set the LOP/LON pins to be inputs or outputs. LO input/output. An external 1x LO or 2x LO can be applied to this single-ended input connector. Alternatively, the internal 1x or 2x LO can be brought out on this pin. The differential LO signal on LOP and LON is converted to a single-ended signal using a broadband 1:1 balun (Macom MABA-007159, 4.5 MHz to 3000 MHz frequency range). The balun footprint on the evaluation board is also designed to accommodate Johanson baluns: 3600BL14M050 (1:1, 3.3 GHz to 3.9 GHz) and 3700BL15B050E (1:1, 3.4 GHz to 4 GHz). Reference input. The input reference frequency for the PLL is applied to this connector. Input resistance is set by R73 (49.9 ). Multiplexer output. The REFOUT connector connects directly to the device's MUXOUT pin. The on-board multiplexer can be programmed to bring out the following signals: REFIN, 2x REFIN, REFIN/2, REFIN/4, Temperature sensor output voltage (VPTAT), Lock detect indicator. Charge pump test point. The unfiltered charge pump signal can be probed at this test point. Note that this pin should not be probed during critical measurements such as phase noise. Loop filter. Loop filter components. Internal vs. external VCO. When the internal VCO is enabled, the loop filter components connect directly to the VTUNE pin (Pin 39) by installing a 0 resistor in R62. In addition, the loop filter components should be returned to Pin 40 (DECL3) by installing a 0 resistor in R12. To use an external VCO, R62 should be left open. A 0 resistor should be installed in R63, and the voltage input of the VCO should be connected to the VTUNE SMA connector. The output of the VCO is brought back into the PLL via the LO IN/OUT SMA connector. In addition, the loop filter components should be returned to ground by installing a 0 resistor in R11. Loop filter return. RSET. This pin is unused and should be left open. Baseband input termination. Termination resistors for the baseband filter of the DAC can be placed on R23 and R3. In addition to terminating the baseband filters, these resistors also scale down the baseband voltage from the DAC without changing the bias level. These resistors are generally set in the 100 to 300 range. USB circuitry bypass. The USB circuitry can be bypassed, allowing for the serial port of the ADRF6702 to be driven directly. P3 (Samtec TSW-104-08-G-S) must be installed, and 0 resistors (R15, R17 and R18) must be removed. Default Condition/Option Settings
EXT LO, T3
T3 = Macom MABA-007159 EXT LO SMA connector = installed
REFIN SMA Connector, R73 REFOUT SMA Connector, R16
FREFIN = 153.6 MHz R73 = 49.9 REFOUT SMA connector = open R16 = open
CP Test Point, R38
CP = open R38 = open See Table 8 R12 = 0 (0402) R11 = open (0402) R62 = 0 (0402) R63 = open (0402) VTUNE = open
C13, C14, C15, C40R9, R10, R37, R65 R11, R12, R62, R63, VTUNE SMA Connector
R2 R23, R3
R2 = open (0402) R3 = R23 = open (0402)
P3 4-Pin Header, R15, R17, R18
P3 = open R15, R17, R18 = 0 (0402)
Rev. 0 | Page 31 of 36
ADRF6702
Figure 53. Main Controls of the Evaluation Board Control Software
Rev. 0 | Page 32 of 36
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ADRF6702
Figure 54. USB Interface Circuitry on the Customer Evaluation Board
Rev. 0 | Page 33 of 36
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ADRF6702 OUTLINE DIMENSIONS
6.00 BSC SQ 0.60 MAX 0.60 MAX
31 30 40 1
PIN 1 INDICATOR
PIN 1 INDICATOR
TOP VIEW
5.75 BSC SQ
0.50 BSC 0.50 0.40 0.30
EXPOSED PAD
(BOT TOM VIEW)
4.25 4.10 SQ 3.95
10
21 20
11
0.25 MIN 4.50 REF
12 MAX
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM
1.00 0.85 0.80
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2
Figure 55. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 6 mm x 6 mm Body, Very Thin Quad (CP-40-1) Dimensions shown in millimeters
ORDERING GUIDE
Model 1 ADRF6702ACPZ-R7 ADRF6702-EVALZ
1
Temperature Range (C) -40C to +85C
Package Description 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board
072108-A
SEATING PLANE
0.30 0.23 0.18
0.20 REF
COPLANARITY 0.08
FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
Package Option CP-40-1
Z = RoHS Compliant Part.
Rev. 0 | Page 34 of 36
ADRF6702 NOTES
Rev. 0 | Page 35 of 36
ADRF6702 NOTES
(c)2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08568-0-4/11(0)
Rev. 0 | Page 36 of 36

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